The technology inside the Ciúnas devices

For all you armchair engineers out there who need to scratch your itch, here's a rundown on some of the components inside the Ciúnas devices and how they're used.

I have always used the best, lowest noise components I could find inside my devices. For instance, I use Cornell Dubilier FCA acrylic film smd capacitors as bypass capacitors because "they excel in attenuating DC power bus noise, and as ripple filters in dc to dc power conversion circuits". Although batteries don't have ripple or DC noise, I use them anyway as a belt and braces approach. Even though these cost 20 times more than the usual ceramic smd capacitors used in this role. I usually mount them right at the power input pins for lowest inductance & most effective position.

What I call ultra low noise stable power others use different terminology. For instance others state:  "Reference Level

Now completely isolated from noise to produce a high-stability Reference Level voltage that generates the signal’s amplitude without variation."

Resized Front Stack of cases.jpg

The range of case sizes used in the various products. From top

  • ISO-DAC case & also used for 5V supercap PS

  • 7V to 12V supercap PS

  • 12V to 15V

  • 15V to 19V

  • 19V to 23V

See here for more pictures​

ISO-DAC block diagram

As seen in the diagrams two low jitter audio clocks are located on a separate board which reclocks the LRCK, SDATA & BCK I2S with the MCLK directly from these audio oscillators signals. This is the optimal place to reclock signals - just before they enter the DAC or SPDIF transceiver chip and produces the cleanest, lowest jitter audio signal possible.. The MCLK is sent back to the Amanero board for its clocking of the I2S signals. This is synchronous clocking, not asynchronous clocking and the best way to avoid clock domain problems when using two different clocks.  

ISO-SPDIF block diagram

ISO Devices

The ISO device add USB isolation in front of the above technology, all incorporated in one case & again powered by battery for lowest & most stable noise possible


previously used A123 LiFePO4 batteries (2.5Amp hours) in all my ISO devices to provide isolated power supplies. These batteries are capable of 120Amps current output for 10 secs or 50Amps continuous output (I've started my car with 4 of them). They act like a huge capacitor with a large reserves of power stored but unlike capacitors these batteries have an internal impedance of 6mOhm, better than almost all capacitors. They don't suffer from chemical reaction 'noise' & in fact, have very low & ultra stable noise well into MHz region. See FAQ for more details.

I now use supercapacitors inside my devices to provide power. These have a similar or higher current output. They are just as stable & low noise as the LiFePO4 batteries. In fact the Nesscap 350F supercapacitors that I use have a lower internal impedance than the batteries which means they can deliver current faster & are possibly even lower noise? 

The Silanna USB isolator is used for USB high speed signal  isolation which uses a capacitive isolation method.

The supercapacitor powers both the input side of the Silanna USB isolation chip - the so-called "dirty" side & the "clean" side. I don't power this "dirty" using the USB 5V as my tests showed that it is an advantage to power it with clean 3.3V isolated battery power.

The main audible improvement comes from the isolation of the USB signals, not the ground connection.

I don't use voltage regulators between supercapacitor & component being powered as I have found that even the best voltage regulators degrade the sound. I surmise that there is some interaction between the output stages of regulators (feedback?) and the component drawing current which causes instability or noise in the regulator. 

Downstream of the USB isolation is a Genesys USB hub chip which reclocks & completely regenerates the USB signal. This is needed after USB isolation as ALL isolator chips add jitter/skew to the signal.

The final technology is that the I2S signal is reclocked by low jitter oscillator just before it enters the final DAC or SPDIF chip

ISO-HUB block diagram